1. Field of the Invention
The present invention relates to a data transfer apparatus, and more particularly, to a data transfer apparatus having a data input mode and a data output mode.
2. Description of the Prior Art
For example, in a semiconductor integrated circuit apparatus, a mode to input data and a mode to output data are necessary in data transfer with a microcomputer. Referring to FIG. 1, there is shown a relevant portion of such a conventional semiconductor integrated circuit apparatus. First, a CE (clock enable) signal, a serial data DA and a clock CK are supplied from a microcomputer 70. When the level of the CE signal is high, a data input mode is set. When the level is low, a data output mode is set.
In the data input mode, the data DA is serially input to an input shift register 76 by the clock CK. The input data is latched once by a latch circuit 77 in synchronism with the fall of the CE signal. During this period, i.e. during the high level period of the CE signal, since an inversion output (low level) of the CE signal inverted by an inverter 75 is applied to an AND gate 78, the AND gate 78 is closed, so that the clock CK is not supplied to an output shift register 81. An AND gate 79 inserted in the output line of the output shift register 81 is also closed.
When the level of the CE signal becomes low, no latch is applied to the latch circuit 77 although the input shift register 76 is operable, so that no data input is performed. The low level CE signal is inverted by the inverter 75 into a high level signal and supplied to the AND gates 78 and 79, so that the output shift register 81 is operable and its output path is conductible through the AND gate 79. Thus, the data processed in the semiconductor integrated circuit apparatus and latched by the latch circuit 80 are serially output through the output shift register 81 and supplied to the microcomputer 70. In FIG. 1, reference numerals 71 to 74 represent terminals of the semiconductor integrated circuit apparatus.
As described above, in the conventional apparatus of FIG. 1, the data input mode is set when the level of the CE signal is high, and the data output mode is set when the level is low. On the other hand, in a conventional apparatus shown in FIG. 2, the data DA includes a data (constituted by several bits) to specify the input mode and the output mode. The data is discriminated by a decoder 82, and based on the discrimination result, a switching circuit 83 switches the input clock to the input shift register 76 or to the output shift register 81. Thereby, the data input mode and the data output mode are set.
However, in the conventional apparatus of FIG. 1, since the data output mode is set when the level of the CE signal becomes low, the output shift register operates in response to the input of the clock CK even when it is unnecessary to output data, so that the power consumption increases and a mis-operation may be caused. In the conventional apparatus of FIG. 2, since the decoder 82 is necessary and it is necessary for the microcomputer 70 to produce a data to specify the input mode and the output mode, necessary software increases and the capacity of a program storing ROM (read only memory) increases.